1 ? fn6655.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. ISL88042 quadruple voltage monitor the ISL88042 is a quadruple voltage-monitoring supervisor combining competitive reset threshold accuracy and low power consumption. this devic e combines popular functions such as power-on reset, unde rvoltage supply supervision, reset signaling and manual reset. monitoring four different supplies in a 8 ld 2x3 tdfn package, the ISL88042 devices can help to lower system cost, reduce board space requirements, and increase the reliability of multi-voltage systems. low v dd detection circuitry protects the user?s system from low voltage conditions, resetting the system when v dd or any of the other monitored power supply voltages fall below their respective minimum voltage thresholds. the reset signal remains asserted until all of these voltages return to proper operating levels and stabilize. two of the four voltage monitors have preset thresholds for either dual 3.3v or one each for one 5v and one 3.3v supplies. users can adjust the threshold voltages of the third and fourth voltage monitors in order to meet specific system level requirements. pinout ISL88042 (8 ld tdfn) top view features ? quadruple voltage monitoring ? fixed-voltage options allow precise monitoring of +5.0v and +3.3v power supplies ? two adjustable voltage inputs monitor voltages > 0.6v ? 95ms nominal reset pulse width ? manual reset capability ? reset signals valid down to v dd = 1v ? immune to power-supply transients ? low 22a maximum supply current at 5v ? pb-free (rohs compliant) applications ? telecom and datacom systems ? routers and servers ? access concentrators ? cable/satellite applications ? desktop and notebook computer systems ? data storage equipment ? set-top boxes ? industrial equipment ? multi-voltage systems 1 2 3 4 8 7 6 5 v dd v2mon gnd rst v dda v4mon v3mon mr epad (gnd) ordering information part number (notes 1, 2) part marking v th1 (v) v th2 (v) temp range (c) package tape & reel (pb-free) pkg. dwg. # ISL88042irthfz-t 4p6 4.60 3.09 -40 to +85 8 ld tdfn l8.2x3a ISL88042irthfz-tk 4p6 4.60 3.09 -40 to +85 8 ld tdfn l8.2x3a ISL88042irteez-t 2p9 2.87 2.95 -40 to +85 8 ld tdfn l8.2x3a ISL88042irteez-tk 2p9 2.87 2.95 -40 to +85 8 ld tdfn l8.2x3a ISL88042irtjjz-t 2p8 2.78 2.86 -40 to +85 8 ld tdfn l8.2x3a ISL88042irtjjz-tk 2p8 2.78 2.86 -40 to +85 8 ld tdfn l8.2x3a notes: 1. please refer to tb347 for details on reel specifications . 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). in tersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020 . data sheet june 8, 2009
2 fn6655.1 june 8, 2009 functional block diagram pin descriptions ISL88042 pin number pin name function 1mr active-low open drain manual reset i nput with internal pull-up resistor 2v dd chip bias input and primary int egrated preset undervoltage monitor 3 v2mon secondary integrated preset undervoltage monitor input 4 gnd ground 5 v3mon adjustable undervoltage monitor input 6 v4mon adjustable undervoltage monitor input 7v dda must be tied to v dd for proper operation 8rst active-low open drain reset output ? v ref v dd por gnd ? v ref v2mon pb rst ? v ref v3mon ? v ref v4mon mr t por ISL88042
3 fn6655.1 june 8, 2009 absolute maximum rati ngs thermal information temperature under bias . . . . . . . . . . . . . . . . . . . . .-40c to +125c voltage on vdd with respect to gnd. . . . . . . . . . . . . . -1.0v to +7v voltage on v3mon, v4mon . . . . . . . . . . . . . . . . . . . . . . -1.0v to 3v voltage on any other pin. . . . . . . . . . . . . . . . . -1.0v to vdd + 0.3v dc output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma recommended operating conditions operating temperature range (industrial) . . . . . . . .-40c to +85c storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c thermal resistance (typical) ja (c/w) jc (c/w) 8 ld tdfn package (notes 3, 4). . . . . 60 8 pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 3. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 4. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications over the recommended operating conditions, unless other wise specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specifi ed. temperature limits est ablished by characterization and are not production tested. symbol parameter test conditions min typ max units v dd supply voltage range 2.0 5.5 v i dd1 v dd supply current v dd = 5.0v 14 22 a i dd2 v2mon input current v2mon = 3.3v 5.5 8 a i dda v3mon, v4mon input current v3mon, v4mon = 1.0v 19 100 na voltage thresholds v th1 fixed voltage trip point for v dd ISL88042irthfz 4.370 4.600 4.830 v ISL88042irteez 2.734 2.872 3.010 v ISL88042irtjjz 2.647 2.78 2.914 v v th1hyst hysteresis of v th1 v th1 = 4.60v 92 mv v th1 = 2.87v 58 mv v th1 = 2.78v 58 mv v th2 fixed voltage trip point for v2mon ISL88042irthfz 2.936 3.090 3.245 v ISL88042irteez 2.815 2.957 3.099 v ISL88042irtjjz 2.725 2.86 3.000 v v th2hyst hysteresis of v th2 v th2 = 3.09v 61 mv v th2 = 2.96v 60 mv v th2 = 2.86v 60 v ref ISL88042irthfz, ISL88042irteez adj. reset threshold voltage v th for v3mon, v4mon 0.572 0.600 0.630 v v ref ISL88042irtjjz adj. reset threshold voltage v th for v3mon, v4mon 0.554 0.581 0.610 v v refhyst hysteresis voltage 12 mv reset v ol reset output voltage low v dd 3.3v, sinking 2.5ma 0.05 0.40 v v dd < 3.3v, sinking 1.5ma 0.05 0.40 v t rpd v th to reset asserted delay 6s ISL88042
4 fn6655.1 june 8, 2009 pin descriptions rst the rst output is an open drain ou tput, which is asserted low whenever the following occurs: 1. the device is initially powered up to 1v or 2. v dd , v2mon, v3mon or v4mon fall below their minimum voltage sense level. mr the mr input is an active low debounced input to which a user can connect a push-button to add manual reset capability or use a signal to pull low. mr has an internal pull-up resistor. v dd the v dd pin is the ic power supply terminal. the voltage at this pin is compared against an internal factory-programmed voltage trip point, v th1 . rst is first asserted low when the device is initially powered and v dd < 1v and then at any time thereafter when v dd falls below v th1 . the device is designed with hysteresis to help prevent chattering due to noise and is immune to brief power-supply transients. v2mon the v2mon input is the second preset monitored voltage that causes the rst output to go low when the voltage on v2mon falls below v th2 . v3mon, and v4mon the vxmon inputs provide monitoring and uv compliance of three additional voltages through resistor dividers. a reset is issued on the ISL88042 if the voltage on any vxmon falls below the internal v ref of 0.6v. . principles of operation the ISL88042 device provides those functions needed for monitoring critical voltages, such as power-supply and battery functions in microprocessor system s. it provides such features as power-on reset control, supply voltage supervision, and manual reset assertion. the inte gration of all these features along with competitive reset threshold accuracy and low power consumption, makes the ISL88042 device suitable for a wide variety of applications needing multi-voltage monitoring. see figure 1 for the ?typical application diagram?. low voltage monitoring during normal operation, the ISL88042 monitors the voltage levels of v dd , v2mon, v3mon and v4mon. if the voltage on any of these four inputs falls below their respective voltage trip points, a reset is asserted (rst = low) to prevent the microprocessor from operating during a power failure or brownout condition. this reset signal remains low until the voltages exceeds the voltage threshold settings for the reset time delay period t por . the ISL88042 allows users to customize the minimum voltage sense level for two of the four monitored voltages. for example, the user can adjust the vo ltage input trip point (v trip ) for the v3mon and v4mon inputs. to do this, connect an external resistor divider network to the vx mon pin in order to set the trip t por por timeout delay v3mon, v4mon < 3v 40 95 150 ms manual reset v mrl mr input voltage low 0.8 v v mrh mr input voltage high v dd - 0.6 v t mr mr minimum pulse width 550 ns r pu internal pull-up resistor 10 k electrical specifications over the recommended operating conditions, unless other wise specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specifi ed. temperature limits est ablished by characterization and are not production tested. (continued) symbol parameter test conditions min typ max units figure 1. typical application diagram v2mon mr pb gnd rst reset v dd ISL88042 signal v3mon v4mon ISL88042
5 fn6655.1 june 8, 2009 point to some other voltage above 600mv according to equation 1: power-on reset (por) applying power to the ISL88042 activates a por circuit, which makes the reset pin(s) active (i.e. rst goes high while rst goes low). these signals provide several benefits: ? they prevent the system microprocessor from starting to operate with insufficient voltage. ? they prevent the processor from operating prior to stabilization of the oscillator. ? they ensure that the monitored device is held out of operation until internal registers are properly loaded. ? they allow time for an fpga to download its configuration prior to initialization of the circuit. the reset signal remains active until v dd rises above the minimum voltage sense level for time period t por . this ensures that the supply voltage has stabilized to sufficient operating levels. manual reset the manual-reset input (mr ) allows the user to trigger a reset by using a push-button switch or by signaling the input low. the mr input is an active low debounced input. reset is asserted if the mr pin is pulled low to less than 100mv for the minimum mr pulse width or longer while the push-button is closed. after mr is released, the reset output remains asserted low for t por (200ms) and then is released. figures 2 and 3 illustrate the ISL88042?s operation. v trip 0.6v = r 1 r 2 / + r 2 (eq. 1) v dd / v2mon mr rst t por v th1/ v th2 1v t por t por >t mr t rpd figure 2. power supply monitoring diagram >t md vxmon rst v th t por t rpd figure 3. voltage monitoring diagram ISL88042
6 fn6655.1 june 8, 2009 the ISL88042eval1z and applications the ISL88042eval1z supports all variants of the ISL88042 devices, enabling evaluation of basic functional operation and common application implementati ons. figure 10 illustrates the ISL88042eval1z in schematic a nd photographic forms. the ISL88042eval1z is populated with the ISL88042irteez (v dd v th1 and v2mon v th2 =2.90v). with adequate bias on the two preset and the two adjustable monitor inputs the rst output will release to pull high indicating that all supplies are compliant for a minimum of t por . for the ISL88042eval1z as shipped, the v dd and v2mon nominal thresholds are as previously noted with the voltage thresholds being monitored by v3mon and v4mon being left open for programming via the non populated resistor dividers. special application considerations using good decoupling practices on bias and other monitoring inputs will prevent transients (i.e. due to switching noises and short duration droops in the supply voltage) from causing unwanted resets. in unusually noisy environments or situations where unwanted signals may be injected into the adjustable vmon inputs, lowering the node impedance and/or positioning a small valued filter capacitor as close to the pin as possible can increase noise immunity. although the internal ISL88042 threshold references are guaranteed over the full temp range, accuracy errors due to external component tolerances and distribution losses will occur. high tolerance resistors and layout for extreme accuracy and critical performance must be considered. typical performance curves figure 4. vdd and v2mon vth vs temperature figure 5. v3mon and v4mon vth vs temperature figure 6. t por vs temperature figure 7. bias current vs temperature 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 -40 -20 0 25 50 85 100 125 temperature (c) avg. vdd and v2mon vth (v) 4.53 4.54 4.55 4.56 4.57 4.58 4.59 4.60 ISL88042irthf vdd ISL88042irthf v2mon ISL88042irtee v2mon ISL88042irtee vdd 592 593 594 595 596 597 598 599 600 601 602 -40 -20 0 25 50 85 100 125 temperature (c) avg. vxmon vth (mv) v4mon v3mon 80 85 90 95 100 105 110 115 120 -40-200 255085100125 temperature (c) t por (ms) 0 2 4 6 8 10 12 14 16 -40 -20 0 25 50 85 100 125 temperature (c) bias current (a) vdd = 5v v2mon = 3.3v ISL88042
7 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6655.1 june 8, 2009 figure 8. ISL88042 t rpd figure 9. ISL88042 t por typical performance curves t rpd = 4.3s 1s/di rst 1v/div vmon = 0.5v/div vmon = 0.5v/div t por = 94ms 20ms/div rst 1v/div figure 10. ISL88042eval1z schematic and photograph mr v2mon rst vdd gnd vdd v4mon v3mon mrst v4mon v4 v3 rst u1 ISL88042 agnd a a vdd v2mon open c1 a r3 open open r5 r4 open r6 open r2 10k v3mon ISL88042
8 fn6655.1 june 8, 2009 ISL88042 package outline drawing l8.2x3a 8 lead thin dual flat no-lead plastic package with e-pad rev 1, 06/09 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.20mm and 0.32mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.15 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail "x" c c 5 6 6 a b 0.75 0.05 0.05 0.20 ref package 2.00 3.00 1.80 +0.1/ -0.15 1.65 + 0.1/ -0.15 0.50 0.25 2.20 1.65 1.80 (8x0.25) 3.00 2.00 (8x0.20) (8x0.40) (8x0.40) (6x0.50) outline
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